1. Field of the Invention
The present invention relates to a field effect transistor and a method for manufacturing the same, and more particularly, to a field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion and a method for manufacturing the same.
2. Discussion of Related Art
With the increasing integration density of semiconductor devices came the reduction in gate length of transistors, and as a cross-sectional area decreases due to the reduction of the gate length, a problem of increase in gate resistance has emerged. Particularly, the characteristics of a GaAs high electron mobility transistor (HEMT), frequently used in communication devices and high-speed computers due to an excellent low-noise characteristic and high operating speed, can be controlled to a large extent by the resistance value of the gate. Therefore, various methods such as a stable low-resistance ohmic process, ultra-fine low-resistance T- or Γ-shaped gate formation, and so forth have been proposed to reduce the resistance value of the gate.
FIGS. 1a to 1f are cross-sectional views illustrating a method for manufacturing a conventional field effect transistor having a T-shaped gate electrode.
Referring to FIG. 1a, an active layer 11 and a cap layer 12 providing source and drain areas and a channel area are formed on a semiconductor substrate 10 in order.
Referring to FIG. 1b, an ohmic metal layer 13 is formed on the cap layer 12 of the source and drain areas.
Referring to FIG. 1c, a multi-layer structure, e.g., photoresist layers 14, 15 and 16 having a triple-layer structure, are formed on the entire surface, and then the photoresist layers 16, 15 and 14 are patterned to form a hole structure shaped like a T-shaped gate electrode. Here, in order to minimize the length of the foot of a gate electrode, the photoresist layer 14 providing an opening for the foot of the gate electrode is generally formed to be thin.
Referring to FIG. 1d, an exposed portion of the cap layer 12 is removed by an etching process that uses the patterned photoresist layers 14, 15 and 16 as a mask. Here, in order to prevent the foot of the gate electrode to be formed from contacting the cap layer 12, the cap layer 12 is etched wider than the exposed portion defined by the photoresist layer 14 so that a recess structure 17 is formed under the photoresist layer 14.
Referring to FIG. 1e, after metal is deposited over the entire surface of the substrate having the recess structure 17, the photoresist layers 16, 15 and 14 are removed by a lift off process to form a T-shaped gate electrode 18.
Referring to FIG. 1f, an insulating layer such as a silicon nitride layer, a silicon oxide layer, etc. is deposited over the entire surface of the substrate having the gate electrode 18 to form a protection layer 19.
As described above, conventionally, a gate electrode is formed in a T or Γ shape using a photoresist layer having a multi-layer structure. In addition, the lower photoresist layer for forming the foot of the gate electrode is formed to be thin, so that the gate electrode is formed to have a small height. However, according to this method, as distance between the head of the gate electrode and the semiconductor substrate decreases, parasitic capacitance increases. And, as the width of the head of the gate electrode is increased in order to reduce the resistance of the gate electrode, the parasitic capacitance increases all the more.
In addition, according to the conventional method described above, since the protection layer is filled in the recess structure when the protection layer is formed, parasitic capacitance between the head of the gate electrode and the semiconductor substrate increases even more. In order to prevent this, the protection layer should be thinly deposited. However, when the protection layer is thinly deposited, it may not provide sufficient protection, which results in deterioration of the characteristics and reliability of the device.